1. Field of the Invention
The present invention relates to a method of defect inspection, and more specifically, to an in-line defect inspection method for daily check.
2. Description of the Prior Art
In the semiconductor manufacturing, some tiny particles and defects, which frequently reduce the performance of integrated circuits, are sometimes formed during various processes unavoidably. Therefore, different inspections are performed on semiconductor devices during the production in order to adjust production parameters, ensuring the reliability and yield of manufacturing processes by preventing the appearances of defects.
Please refer to FIG. 1, which represents a flow chart of semiconductor manufacturing according to the prior art. As shown in FIG. 1, a plurality of cassettes, C1, C2 . . . to C10, is provided, and each of the cassettes C1 to C10 comprises a plurality of wafers. Then the data of cassettes C1 to C10 is recorded in a process control server (not shown) by a process engineer, and the process control server activates the production procedure in which cassettes C1 to C10 are involved afterward. Based on the production procedure installed in the process control server, a plurality of processes P1 to Pn are performed on cassettes C1 to C10 to form various devices on surfaces of the wafers. Either one of processes P1 to Pn is a semiconductor process, such as a thin film deposition process, an ion implantation process, an etching process or a lithography process. In addition, as shown in FIG. 1, tools 10a and 10b are utilized to perform process P1, tools 20a, 20b and 20c are utilized to perform process P2, and tool 30a is utilized to perform process Pn.
Generally, each manufacturing tool has its inspection procedure, such as a daily check procedure, in order to maintain the reliability and stability of manufacturing processes it performs. Please refer to FIG. 2, which represents a flow chart of a daily check procedure. As shown in FIG. 2, the daily check procedure comprises the following steps of:
step 40: start;
step 42: provide a bare wafer W;
step 44: perform a defect inspection process on the bare wafer W to obtain a first defect inspection information with the locations and number of defects on the surface of the bare wafer W;
step 46: install the bare wafer W into a manufacturing tool needing to be inspected, such as tool 20a, and perform process P2 on the bare wafer W;
step 48: perform a defect inspection process on the bare wafer W to obtain a second defect inspection information with the locations and number of defects on the surface of the bare wafer W;
step 50: compare the first defect inspection information with the second defect inspection information to determine whether the tool 20a can be used to perform process P2, such as by determining whether the difference of the numbers of defects on the bare wafer W provided in the first and second defect inspection information is within an allowable specification, i.e. less or equal to 30; and
step 52: end.
However, the cost of bare wafer, especially a 12″ wafer, is so high that the production cost would be severely increased if we use it for daily check. In addition, many integrated defects occur only after a series of processes and therefore can not be found on a bare wafer. As a result, the daily check procedure turns out to be ineffective. Moreover, the production tool, such as tool 20a, cannot simultaneously be inspected by the daily check procedure in FIG. 2 and perform manufacturing processes on product wafers. Therefore, in order to maintain the utilization of tool capacity at a certain level, the daily check procedure is rarely daily performed, leading to a inefficient monitor of the tool.
In addition to the inspection towards the tool, some defect inspection processes, such as defect inspection processes D1 and D2 shown in FIG. 1, are optionally performed to inspect the manufacturing processes in FIG. 1, ensuring the stability of the semiconductor manufacturing as well as the reliability of the product. Moreover, some cassettes among the cassettes C1 to C10, such as cassettes C3, C5, C6 and C10 in FIG. 1 for instance, are selected by the process control server as sampling cassettes to form a sample lot prior to the performance of the manufacturing processes on the cassettes C1 to C10, wherein wafers comprised in each of the sample cassettes are utilized to perform the in-line defect inspection method. Please refer to FIG. 3, which represents the flow chart of an in-line defect inspection method towards a manufacturing process, such as the process P2 in FIG. 1, according to the prior art. As shown in FIG. 3, the in-line defect inspection method according to the prior art comprises the following steps of:
step 60: start;
step 62: receive a sampling cassette (for example, sampling cassette C3);
step 64: randomly install sampling cassette C3 into either one of the tools 20a, 20b or 20c and performing the process P2 on each of the wafers in the sampling cassette C3;
step 66: perform the defect inspection processes D2 on portions of the wafers in the sampling cassette C3 and determine whether the characteristics of defects found on the inspected wafers, such as the number of defects, are within an allowable specification, less than 100 for instance, in order to subsequently proceed either step 68, if the characteristics of defects found on the inspected wafers are within the allowable specification, or step 70, if the characteristics of defects found on the inspected wafers are out of the allowable specification;
step 68: perform a subsequent manufacturing process;
step 70: inform process engineers responsible for process P2; and
step 72: end.
As shown in FIG. 3, the operators randomly install the sampling cassettes C3, C5, C6 and C10, one at a time, into one or more not-in-production tools among tools 20a, 20b and 20c at the time of the installation. As a result, some tools may not be installed with any sampling cassette and therefore are not inspected. For example, tools 20a and 20b may be excluded from the defect inspection process in case that all of the sampling cassettes C3, C5, C6 and C10 are installed into tool 20c as a result of a coincidence.
An alternative solution to eliminate the disadvantage of the in-line defect inspection method revealed in FIG. 3 frequently adopted by operators is to perform a daily check by using product wafers. Please refer to FIG. 4, which represents the flow chart of the daily check by using product wafers according to the prior art. As shown in FIG. 4, the daily check comprises the following steps of:
step 80: start;
step 82: randomly select an in-line cassette, i.e., cassette C1;
step 84: install the cassette C1 into a tool waiting for inspection, for example, tool 20a, and performing process P2 on each of the wafers in the cassette C1;
step 86: perform a defect inspection process on portions of the wafers in the cassette C1 and determine whether the characteristics of defects found on the inspected wafers, such as the number of defects, are within an allowable specification, less than 100 for instance, in order to subsequently proceed either step 88, if the characteristics of defects found on the inspected wafers are within the allowable specification, or step 90, if the characteristics of defects found on the inspected wafers are out of the allowable specification;
step 88: perform a subsequent manufacturing process;
step 90: inform process engineers responsible for process P2; and
step 92: end.
Generally, operators randomly choose two cassettes everyday to perform the daily check revealed in FIG. 4 on each of the tools utilized in semiconductor manufacturing. However, the chosen cassettes sometimes do not contain the defect information about previous processes since they are not necessarily sampling cassettes. Therefore, operators need to use a detector, such as a scanning electron microscopy (SEM), to analyze defects in order to determine whether the inspected tool is abnormal. The yield rate may be lowered due to inadequate judgment of operator towards the inspected tool caused by the improper operation of the SEM. Moreover, the methods in FIG. 3 and FIG. 4 are performed by utilizing product wafers, which frequently leads to redundant inspection efforts. As a result, the production lead-time and labor cost are both increased.